1. Field of the Invention
The present invention relates to manufacturing methods for a microelectronic interlayer dielectric structure, and more particularly relates to improvement in planarization and reduction of void formation in a multilayer metal system where the aspect ratio of first layer metal thickness to first layer metal spacing is on the order of 0.7.
2. Description of Related Art
A common practice in the manufacture of microelectronic devices and integrated circuits is to protect the semiconductor surface, as well as the metal layer surfaces with a covering insulator layer. These insulator layers are sometimes referred to as dielectric layers, or as passivation layers. Modern microelectronic semiconductor devices often require multiple layers of metal, one crossing over the other and separated by an interlayer dielectric. Interlayer connection points are provided through openings, or contact holes, formed for that purpose in the dielectric layers.
As metal spacing decreases to meet the requirements of VLSI/ULSI processing and circuit design, several problems begin to appear as a result of the non-planar intermetal dielectric surface. To prevent such problems it is well-known to planarize the intermetal dielectric.
A prior art method of manufacturing microelectronic devices having multilayer wiring, is shown in FIG. 2. A silicon substrate 11 has a field oxide layer 12 formed upon it. Subsequently a first metal layer 13 is formed on field oxide layer 12. In this example, metal layer 13 was formed by sputtering an Al alloy to a thickness of about 0.5 to 1.0 .mu.m. After sputtering, first metal 13 was patterned to the required shape by photoetching. Silicon oxide film 24 was then grown in the vapor phase by plasma or heat reaction of a combustible gas such as SiH.sub.4 and O.sub.2 or N.sub.2 O, as an interlayer insulator, to a thickness typically on the order of 0.5 to 0.8 .mu.m. Because of the need to planarize the interlayer dielectric, a spin-coated glass 16 of silanol and P.sub.2 O.sub.5 dissolved in an alcohol is formed over silicon oxide film 24. Next, annealing at a temperature that would not damage first metal 13 was performed. The concentration of P.sub.2 O.sub.5 mixed into the spin-coated glass was on the order of 1 to 5 mol %, and its purpose was to raise the stress relaxation of the spin-coated glass and the crack resistance effect.
After formation of the interlayer dielectric structure, contact holes were etched through glass film 16 and silicon oxide film 24. Contact etch was typically performed by reactive ion etching using gases such as CF.sub.4, CHF.sub.3 or C.sub.2 F.sub.6.
A second metal layer 19 was formed by sputtering an Al alloy and patterning by well-known, conventional photoetching techniques. A passivation film 20 was formed over second metal 19, and finally a bond pad opening was formed in passivation film 20 for making external connections.
As the first-layer metal-to-metal spacings were decreased to achieve greater packing density, prior art devices experienced cusping of silicon oxide films 24 formed in the spaces between first-layer metal lines when silicon oxide films 24 were grown in the vapor phase with SiH.sub.4 and combustible gas. Even though the prior art teaches the use of spin-on-glass to fill the cusps and troughs of the silicon oxide films 24, it has been found by the inventor that as metal-to-metal spacing decreases and the metal height to spacing aspect ratio reaches approximately 0.7, voids within the spin-on-glass regions are formed. It has also been found that where liquid spin-on-glass accumulates in U-shaped troughs, or channels, between first-layer metal lines, cracks in the spin-on-glass regions tend to form during subsequent processing steps. Crack 21, as shown in FIG. 2, is illustrative of this phenomenon. Both cracks 21 and voids 22 lead to reliability and yield losses.
Reliability and yield problems also arise when contact holes through intermetal dielectrics are etched anisotropically and therefore the side surfaces of the contact holes are nearly vertical. Vertical contact hole sidewalls result in poor step coverage by second metal layer 19. Poor step coverage in turn produces thin metal which is susceptible to deterioration due to electromigration.
It would be desirable to provide a taper, or slope, to the contact hole sidewalls to overcome the problem of poor second metal step coverage. While a high temperature reflow of spin-coated glass 16 might provide such a taper, this process step is not possible because first metal 13 cannot tolerate the temperature required to reflow spin-coated glass 16. There have been attempts to give an isotropic taper to the contact holes by means of wet etching with an HF system aqueous solution. Unfortunately, this HF etching cannot be used with the above-described interlayer dielectric as line widths and spacings are decreased, because the etch rate with the HF system aqueous solution is high and there is an unacceptable amount of side etching.
Another prior art method of manufacturing microelectronic devices having multiple layers of interconnect is disclosed in U.S. Pat. No. 4,775,550 to Chu et al. There, a three layer intermetal dielectric having a first dielectric material formed over a first conductive layer, a spin-on-glass layer which fills the low-lying regions of the first dielectric material, and a second dielectric material which provides a planar surface and isolates the spin-on-glass from any metal, is described. The problem with such a process is that spin-on-glass regions thicker than 0.4 .mu.m tend to form cracks.